As a Physical Design Intern, you
will be responsible for but not limited to the following:
You will be a member of the Physical Design team
designing the next generation high-performance AI chips in leading edge
CMOS process technology, targeted at cloud training/inference markets.
You will collaborate with senior physical design
engineers to build blocks, and do develop, maintain, enhance design flows.
And make deliver for blocks/modules from TRL to GDSII.
You will also collaborate with front-end designers to
optimize designs based physical design status to close both timing and
congestions.
Qualifications
BS degree or equivalent practical experience. MS in
ME/EE/CS is preferred.
Knowledge of VLSI design include physical design flow
is a strong plus.
Good scripting skills in Tcl, Python, Perl is a strong plus.
Knowledge of semiconductor process is a plus.
Familiar with Linux/Unix system, and generate operation
commands is a plus.
Strong problem solver, communicator and team player.